1. Field
This disclosure relates generally to systems and methods for providing output clock signal, and more specifically, to systems and method for dividing clock signals in electronic circuits.
2. Related Art
In many electronic systems, a clock signal is used to synchronize the various circuits. In complex systems, multiple clock signals are used where, conveniently, one main (high frequency) clock signal is divided to clock signals of lower frequencies wherever needed. It is noted that the dividing of a clock signal is a common term for the processing a first clock signal of a first frequency, to provide a second clock signal of a second frequency lower than the first one, wherein the ratio between the two frequencies is a rational number, and conveniently a natural number. The dividing of clock signals to clock signals of lower frequencies is conveniently carried out by electronic components known a clock dividers, and complex systems usually include a large number of clock dividers.
The power consumption of each of these clock dividers is proportional to the frequency of the input (main) clock signal. In many devices the clock generator unit consumes a substantial portion of the power consumed by the whole device.
FIG. 1 is a block diagram of prior art system 1400 for providing two output clock signals, 1194 and 1294. Conveniently, prior art system 1400 is a part of an electronic system, and, is implemented on a semiconductor chip. Prior art system 1400 includes first clock divider 1100 that is adapted to receive input clock signal 1492, and to provide first divider output clock signal 1194 having a frequency that is lower than a frequency of input clock signal 1492 (in the example illustrated, a having frequency which is half the frequency of input clock signal 1492); and second clock divider 1200, adapted to provide second divider output clock signal 1294 having a frequency that is lower than the frequency of input clock signal 1492 (in the example illustrated, a having frequency which is one quarter of the frequency of input clock signal 1492). It is noted that first clock divider 1100 may be similar to second clock divider 1200.
It is clear to a person who is skilled in the art that the power consumption of second clock divider 1200 is relatively high, as it receives as input a clock signal having a frequency that is four times the frequency of the required second divider output clock signal 1294, while a clock signal having a frequency which is only twice as much is available in prior art system 1400 (i.e. first divider output clock signal 1194).
There is a growing need to reduce the power consumption of a clock generation unit. Such power reduction can reduce the heating of a system and can lengthen the duration between battery replacement or battery recharging operations.